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Base Compensation$98,400 - $164,000
Location & ModeNiskayuna
Seniority LevelSenior (1+ yrs)
Industry CategoryQuantitative Finance & Tech
Job Description & Responsibilities
Role Summary & Application Notice
This opening for FPGA Design - Lead Research Engineer "CLEARANCE REQUIRED" at GE Vernova was indexed directly from the employer's official careers portal.
To ensure candidates review the exact, up-to-date role qualifications, team details, and direct submission instructions, full job specifications are hosted on GE Vernova's official portal.
View & Apply on GE Vernova Career PortalPosition Specifications
- Organization
- GE Vernova
- Location
- Niskayuna
- Role Seniority
- Senior
- Compensation Status
- $98,400 - $164,000
Interested in this role?
Applications are submitted directly to GE Vernova.