Job Details:

Job Description: 

Intel is seeking a senior software engineer for the Silicon Chassis team. In this technical hands-on leadership role, you will help define end-to-end automation strategy and lead development of the chassis automation tool. Chassis refers to non-compute infrastructure in any soc, which provide essential platform services and typically include interconnects, protocol bridges, clock/reset/power, security, debug/trace/analytics (DTA), RAS error logic, address maps, firmware tables etc. The chassis automation tool will collect user requirements, and translate these requirements into chassis parameters, topology and generate RTL, register definitions, integration and verification collateral for the chassis using highly parameterized and configurable sub-components.

You will work directly with chassis architecture, RTL design, verification, and SOC integration teams to encode the architectural rules of the interconnect and develop a reliable, testable automation framework. You will also mentor the junior engineer joining alongside you. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.

Why This Role Is Exciting

Build a brand new automation platform by defining the tool, schema, and methodology from the ground up
Directly influence next-generation SoC chassis architectures and delivery
Collaborate across architecture, RTL, DV, and SoC integration teams
Drive technical direction and establish best practices with broad organizational impact

Key Responsibilities
Architect, design, and implement a new chassis automation tool to meet requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibility.
Analyze chassis and interconnect architecture specifications, along with high-level SoC requirements, and build tooling and infrastructure to translate these requirements into generated outputs such as RTL, RDL, verification collateral, timing, and integration artifacts.
Develop automation flows that convert architectural intent into concrete implementations, including topology generation, parameter derivation, register definitions, and associated collateral.
Integrate with frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (e.g., RTL, Verilog, SDC, RDL), ensuring correctness and consistency.
Enable Power, Performance, and Area (PPA) optimization loops by building automation and analysis capabilities that evaluate design trade-offs and guide configuration decisions.
Work closely with architecture, RTL design, verification, and SoC integration teams to ensure the tool accurately captures requirements and produces outputs that meet downstream expectations.
Participate in and contribute to technical reviews with cross-functional stakeholders, incorporating feedback to improve tool capabilities, usability, and quality.
Drive end-to-end execution from initial concepts and specifications through development, deployment, and ongoing maintenance of the automation framework.
Lead delivery of the tool and associated outputs to multiple internal customers, balancing competing requirements, schedules, and priorities while maintaining high quality.
Collaborate across organizational boundaries and contribute beyond immediate role scope when needed to unblock execution and ensure overall program success.
Mentor and guide engineers, helping establish best practices in software design, testing, and maintainability, and elevating overall team effectiveness.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field, with 9+ years of experience in CAD/EDA tooling, design automation, or semiconductor development.
Strong proficiency in Python or similar language, with proven experience of building scalable, maintainable software systems and frameworks rather than one-off scripts.
Solid understanding of digital SoC design concepts, including RTL hierarchy, synthesis flows, and parameterized IP design.
Experience designing and validating structured schemas using formats such as JSON or YAML.
Working knowledge of SystemVerilog to understand and validate generated design outputs.
Experience with templating systems or code generation frameworks used for structured RTL or collateral generation.
Strong software engineering fundamentals including version control (Git), code reviews, unit/integration testing, and CI/CD practices.

Preferred Qualifications:
Experience with Network-on-Chip (NoC) architectures or high-performance interconnect protocols such as AXI, CHI, PCIe, UCIe, or similar.
Familiarity with IP packaging, configuration, and integration methodologies, including standards such as IP-XACT.
Exposure industry EDA tools and design flows.
Knowledge of graph-based algorithms or data structures relevant to topology generation, connectivity modeling, or routing problems.
Prior experience working in a semiconductor product development environment, such as CAD, RTL design, or verification.
Experience in GUI development
Ability to interpret architecture or micro-architecture specifications and translate them into robust software implementations.
Excellent communication, problem-solving, and organizational skills, with a track record of delivering high-quality solutions on schedule.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

Virtual India

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.