Job Details:

Job Description: 

The Role and Impact
As an Analog Circuit Design Engineer, you will design, develop, and optimize cutting-edge analog and mixed-signal circuits in advanced process nodes for DDR IP. Your day-to-day responsibilities will include creating innovative designs, simulating circuit behavior, and collaborating with cross-functional teams to ensure high-performance results. Your contributions will play a key role in developing robust, power-efficient designs that meet industry standards and drive Intel's leadership in DDR IP.

Key Responsibilities

• Design and innovate mixed-signal circuits such as high-speed transmitters, receivers, equalizers, DLLs, clock distribution, on-die voltage regulators, and reference blocks.
• Perform circuit simulations to ensure designs meet power, performance, area, timing, and yield goals.
• Create and execute test plans to validate functionality, performance, and reliability of designs against microarchitecture specifications.
• Work with the layout team to optimize circuit designs for functionality, robustness, and electrical capabilities.
• Develop CBB collateral for PHY-level integration, including timing library files and behavioral models (BMOD).
• Conduct mixed-signal verification for CBB blocks and support integration into larger systems.
• Participate in design reviews and collaborate with cross-functional teams to identify and resolve design challenges.
• Utilize industry-standard tools such as Cadence ADE, Spectre, AMS verification, and StarRC for design and analysis.

Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Microelectronics, or a related field with 7+ years of industry experience in analog and mixed-signal circuit design, or Master's degree with 5+ years of relevant experience, or PhD with no prior industry experience.

• Demonstrated expertise in analog circuit design, including high-speed TX/RX blocks, DLLs, LDOs, and power optimization.

• Proficiency in circuit simulation tools (e.g., Cadence Spectre, AMS) and verification methodologies.

• Experience with JEDEC LPDDR/DDR specifications and DDR protocols.

• Programming skills in Python or Perl for design automation and verification tasks.

Preferred Qualifications

• Cross-discipline knowledge in RTL/System Verilog, static timing analysis, floor-planning, metal-routing, and power-grid optimization.

• Familiarity with post-silicon validation and production challenges in advanced technology process nodes.

• Strong problem-solving skills, group collaboration abilities, and a commitment to disciplined execution.

• Passion for innovation and continuous learning in analog and mixed-signal design.

We invite you to bring your expertise and creativity to our team, where you will have the opportunity to push the boundaries of what's possible in analog circuit design. Join us in shaping the future of technology.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.