Physical Design Lead

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THE ROLE:

As a member of the CT India Physical Design team, you will play a key role in enabling successful implementation of advanced Chiplet, Testchip, and high-performance SoC designs through close collaboration with Package, Signal Integrity, and Physical Design teams.

In this position as a Package Interface Design Engineer, you will serve as the critical link between Package Engineering and Physical Design teams, driving package-aware implementation from early planning through tapeout. You will work closely with package architects, physical design leads, floorplanning engineers, and chiplet integration teams to define and implement bump maps, package interfaces, die-to-die connectivity, and package-driven physical constraints.

This role offers an exciting opportunity to work on next-generation packaging technologies and chiplet-based products in advanced process nodes, helping ensure seamless integration between silicon and package while meeting performance, power, reliability, and manufacturability requirements.

THE PERSON:

You are a highly motivated engineer with strong knowledge of physical design and semiconductor packaging concepts. You possess a solid understanding of package requirements and their impact on silicon implementation, floorplanning, I/O planning, power delivery, and chip-package co-design.

You are comfortable working across multiple engineering disciplines and can effectively coordinate with Package Design, Signal Integrity, Power Integrity, Design, and Physical Design teams to deliver optimized package interfaces. You have strong communication skills, attention to detail, and the ability to drive technical decisions in a fast-paced development environment.

KEY RESPONSIBILITIES:

• Own and drive bump planning activities for Chiplet, Testchip, and SoC designs in collaboration with Package Engineering teams.
• Define and implement package-aware floorplanning constraints, I/O planning, bump maps, and die interface requirements in the physical design database.
• Work closely with package teams to understand package architecture, routing layers, power delivery requirements, escape routing limitations, and assembly constraints.
• Develop optimized bump assignments considering package technology, signal integrity, power integrity, manufacturability, and cost requirements.
• Collaborate with Physical Design teams to ensure package interfaces are accurately implemented and maintained throughout the design cycle.
• Drive chip-package co-design activities for advanced packaging technologies, including 2.5D, 3D, organic substrate, and silicon interposer-based solutions.
• Support power delivery network planning and package-related implementation requirements to achieve robust IR/EM and power integrity closure.
• Work with SI/PI teams to address package-related electrical challenges and improve overall system performance.
• Participate in package reviews and design convergence meetings, ensuring package and silicon requirements are aligned.
• Develop automation, methodologies, and best practices for bump planning, package interface implementation, and chip-package integration flows.
• Support package-related signoff reviews and contribute to successful tapeout execution.

PREFERRED EXPERIENCE:

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
• 12+ years of industry experience in Package Design, Chip-Package Co-Design, or related semiconductor implementation domains.
• Strong understanding of semiconductor packaging technologies, including Flip-Chip, FCBGA, 2.5D/3D packaging, silicon interposers, and chiplet-based architectures.
• Hands-on experience with bump planning, I/O planning, package interface design, and package-driven floorplanning.
• Good understanding of package routing constraints, escape routing methodologies, power distribution, signal integrity, and power integrity concepts.
• Experience working with Physical Design flows and implementation tools for floorplanning, PnR, and physical verification.
• Familiarity with package design tools and data exchange formats between package and silicon implementation environments.
• Understanding of IR/EM analysis, package parasitics, timing impact, and package-aware design optimization.
• Proficiency in scripting languages such as Tcl, Perl, Python, or Shell for flow automation and productivity enhancement.
• Excellent communication, collaboration, and problem-solving skills with the ability to work effectively across geographically distributed teams.
• Experience with Chiplet architectures and heterogeneous integration technologies is highly desirable.

ACADEMIC CREDENTIALS:

• B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering.
• Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 4 tape-outs.
• Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.