HPC Engineer, Compiler

Job Description

As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.
This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications..

【Job Description】
・Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
・Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
・Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
・Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
・Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
・Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
・Mentor senior engineers and set technical direction without people‑management responsibilities

【Impact & Differentiators】
Renesas’ Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards.  An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric — directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.

Qualifications

【Must-Have】
・MS/PhD (or equivalent experience) in Computer Science, EE, or related field
・Deep experience building AI compilers, accelerator backends, or graph optimization frameworks
・Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators
・Experience with MLIR, LLVM, TVM‑like systems, or proprietary compiler IRs
・Excellent C/C++ and Python skills
・Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models)
・Strong communication skills are required, e.g. agile development experience in Scrum team (Product Owner or Scrum Master)

【Nice-to-Have】
・Experience with automotive or safety‑critical systems
・Background in heterogeneous SoCs (CPU/GPU/DSP/NPU)
・Performance modeling or hardware–software co‑design experience

Additional Information

ルネサスは、「To Make Our Lives Easier（人々の暮らしをより豊かで快適にする）」というPurposeのもと、組込み半導体ソリューションを提供するグローバル企業です。世界30か国以上で活躍する21,000人を超えるエンジニアや課題解決のプロフェッショナルとともに、自動車、産業、インフラ、IoT分野における世界最先端のテクノロジー開発に携わり、より安全で、健康的で、環境にやさしく、スマートな未来の実現に貢献しています。 

ルネサスでは、「TAGIE（Transparent、Agile、Global、Innovative、Entrepreneurial）」を企業文化の中核としています。TAGIEは、私たちの働き方や成長のあり方、そしてPurposeの実現に向けた取り組みを支える共通の価値観です。この協調的な精神と挑戦するマインドセットが、半導体技術を通じた産業の変革と、世界中の人々の暮らしへの貢献を可能にしています。 

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