Analog Mask Design Engineer

What you'll be doing:

• Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 2nm, 3nm, 5nm, 7nm and lower nodes following industry best practices.

• Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.

• Drive the identification and resolution of complex physical design issues in layouts, mentoring junior engineers in established methodologies.

• Development of analog layouts, leading solving efforts and driving optimization for performance, area, and manufacturability.

• Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.

• Excel in resource management, representing the team in technical discussions with customers

• Lead and perform full custom layout of analog/mixed-signal blocks such as op-amps, bandgaps, ADCs, DACs, LDOs, Voltage Regulators etc.

• Ensure design quality by adhering to matching, symmetry, and parasitic sensitivity requirements.

What we need to see:

• 2+ years of experience in high performance analog layout in advanced CMOS process.

• BE/M-Tech in Electrical & Electronics or equivalent experience.

• Thorough knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.

• Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)

• Experience with floor planning, block level routing and macro level assembly.

• Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.

• Demonstrated experience with analog layout for silicon chips in mass production.

• Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.

• Experience working in distributed design team is a plus.

We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

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