Senior ASIC Verification engineer
NVIDIANVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!
What you'll be doing:
- Understand architecture/design and write test plans that are efficient yet exhaustive in coverage.
- Development of test environment such as creation/modification of testbench, updates to software sequences, creation/integration of checkers from UV.
- Execute the test plan, review results with arch/design teams for final signoff.
- Close collaboration with Emulation/FPGA teams to enable our tests and verify the tests on post silicon.
- Innovative optimizations to reduce simulation time and improve verification work flows.
- Work with HW architects and designers to make the right implementation choices to optimize the whole pipeline.
- B.Tech/M.Tech or equivalent experience.
- 4+ years of relevant experience.
- Expertise in verification at sub-system/SOC level and expertise in Verilog and SystemVerilog.
- Expertise in debugging functional and toggle coverage.
- Some experience in UVM is good to have.
- Proficiency in grasping feature requirements for intricate features at the system level and devising test plans to validate them.
- Strong problem-solving skills.
- Strong interpersonal and team building skills with proficiency in written and verbal communications.
- Grasp of system architecture concepts in the context of fullchip verification, like interrupts, error collators, handshakes, IO handling etc.
- Expertise in protocols like APB/AXI/CHI.
- Experience with JTAG and DFT concepts like mbist/lbist.
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