Senior Physical Design Engineer – DPG Layout
MicronOur vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Role and Responsibilities
Execute physical design implementation for SoC blocks and large digital sub-blocks, including floorplanning support, placement, CTS, routing, and physical optimization, to meet power, performance, and area (PPA) targets.
Drive block-level timing closure (setup/hold) across multi-mode, multi-corner (MMMC) scenarios, working closely with STA, RTL, and integration teams to resolve timing issues efficiently.
Implement and debug clocking, reset, and power intent (UPF/CPF) for assigned blocks, ensuring correctness and alignment with SoC integration requirements.
Perform physical verification and signoff checks, including DRC/LVS, antenna, IR drop, EM, noise, and timing, and systematically resolve violations with guidance from senior or staff engineers.
Support tape-out activities through ECO implementation, closure tracking, signoff reviews, and documentation, ensuring deliverables meet quality and schedule expectations.
Collaborate with CAD, methodology, and technology teams to debug PD tool or flow issues and adopt approved methodologies for advanced nodes.
Contribute to productivity and quality improvements by developing scripts, automation, or checks that reduce manual effort and improve turnaround time.
Participate in design and build reviews, sharing learnings, best practices, and root-cause analyses from implementation and signoff cycles.
Assist in post-silicon debug by correlating layout, timing, and power analysis with silicon observations when required.
Job Requirements
6+ years of hands-on experience in physical design implementation for complex SoCs or large digital blocks.
Strong experience with block-level timing analysis and closure, including MMMC setup and hold closure.
Experience working on advanced process nodes (e.g., 7nm, 5nm, or equivalent), with understanding of node-dependent PD challenges.
Proficiency with industry-standard P&R tools such as Cadence Innovus and/or Synopsys IC Compiler II.
Hands-on experience with physical verification and signoff, including DRC, LVS, antenna, and related foundry checks.
Working knowledge of power integrity and reliability analysis, including IR drop, EM, noise, and crosstalk.
Solid understanding of digital design fundamentals, enabling effective collaboration with RTL and architecture teams.
Experience using scripting and automation (Tcl, Python, or similar) to improve efficiency and debug productivity.
Exposure to AI-assisted tools or data-driven techniques for debugging, optimization, or flow efficiency is a plus.
Ability to mentor junior engineers on block ownership, PD flows, and best practices.
Education
B.Tech in Electronics, Electronics & Communication, or VLSI Engineering, or equivalent experience
M.Tech in VLSI Design, Microelectronics, or Electronics Engineering
About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.
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