Job Details:

Job Description: 

The Role and Impact

• As a Layout Design Engineer, you will be responsible for creating custom layout designs for analog blocks, complex digital and mixed-signal blocks, standard cell libraries, and memory compilers. In this role, you will perform detailed physical array planning, layout optimization, and verification to ensure compliance with design rules and reliability standards. Your work will directly contribute to the development of cutting-edge technologies, enabling innovative products and solutions. 
• Business Group
• Join Intel's team focused on advancing silicon design and development for leading-edge technology. This group drives innovation in layout design, ensuring high-quality and efficient solutions that enable Intel's strategic goals. By collaborating with cross-functional teams, the group plays a key role in delivering impactful results for Intel's next-generation technology. 
• Key Responsibilities
• - Develop and optimize custom layout designs for analog, digital, and mixed-signal blocks, including memory compilers and standard cell libraries.
• - Perform detailed physical array planning, area optimization, and critical wire analysis.
• - Conduct layout verification, including design rule checks (DRC), layout versus schematic (LVS), and reliability analysis such as electromigration and voltage drop (IR).
• - Utilize custom placement and routing tools to construct high-quality layouts efficiently.
• - Provide feedback to circuit design engineers regarding feasibility studies and implement circuit enhancement requests.
• - Innovate and drive new layout methodologies to improve productivity and ensure design quality.
• - Debug and troubleshoot issues related to layout design, tool flows, and methodologies.

Qualifications:

• Minimum Qualifications
• - Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 0-1 years of hands-on experience in layout design through internships, academic projects, coursework, or hands-on training OR a Master's degree in a relevant field with no prior professional experience.
• - Proficiency in using EDA tools such as Cadence Virtuoso for layout design and verification.
• - Strong understanding of CMOS circuit design concepts and layout principles.
• - Knowledge of layout verification tools like Calibre DRC and ICV. 
• Preferred Qualifications
• - Familiarity with scripting languages such as TCL, Python, or Perl for design automation.
• - Exposure to designing with advanced technology nodes and optimizing layouts for Power, Performance, and Area (PPA).
• - Ability to collaborate effectively with cross-functional teams and demonstrate problem-solving skills.
• - Passion for innovation and a strong commitment to delivering high-quality results.
• We invite you to bring your skills and enthusiasm to Intel, where you can contribute to groundbreaking technologies and shape the future of innovation.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.