Job Details:

Job Description: 

Join Intel's Wireless Communication Solutions (WCS) team as a Logic Design Engineer, where you'll contribute to next-generation connectivity products that power ultra-fast, low-latency wireless experiences for millions worldwide. As part of our world-class Silicon division, you'll drive wireless connectivity chip development from early-stage definition through tape-out, leveraging cutting-edge AI-assisted design methodologies and AI-enhanced optimization tools.

Key Responsibilities: Develop logic design, RTL coding, and simulation for IP blocks, functional units, and subsystems integrated into full chip designs. Participate in architecture and microarchitecture definition while applying AI-driven optimization strategies to meet power, performance, area, and timing requirements. Review verification plans, resolve RTL test failures, and ensure design correctness using AI-powered debugging and analysis tools.
Support SoC customers for seamless IP integration and drive quality assurance compliance for smooth IP-SoC handoff. Lead complex, end-to-end tasks with full ownership from concept to delivery.

Qualifications:

Minimum Requirements:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 4+ years of experience in RTL design, logic development, and system architecture
• Excellent communication skills and ability to work effectively in team environments
• Proficiency in SystemVerilog and Verilog coding with strong digital design fundamentals
• Hands-on experience with microarchitecture debugging, simulation environments, and testbench development
• Deep knowledge of SoC clocking architectures and integration methodologies
• Proven hardware design expertise with exceptional technical problem-solving abilities

Advantage Qualifications:

• Knowledge in clock domain crossing, clock gating, and low-power design techniques

• Master's degree in Electrical Engineering, Computer Engineering, or equivalent with 3+ years of experience
• Advanced expertise in microarchitecture development and system-level design optimization (PPA: Power, Performance, Area)
• Experience with industry-standard design flows, timing analysis, and physical implementation considerations
• Strong technical documentation skills and proven track record of successful cross-functional collaboration
• Excellent communication abilities with demonstrated leadership potential in complex project environments

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Israel)

Primary Location: 

Israel, Haifa

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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