Job Details:

Job Description: 

• Lead Structural Design / physical design Implementation of Custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to fix violations for current and future product architecture.
• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
• Optimizes design to improve product level parameters such as power, frequency, and area.
• Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

Minimum Qualifications:
• Bachelor's/master's degree in electrical / computer engineering, Computer Science, or in a STEM related field of study.
• Experience in leading small team of engineers.• 14+ years of experience with complex ASIC/SOC Implementation.
• Experience in system and processor architecture.
• Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.
• Experience with System Verilog/SOC development environment.
• Experience in scripting languages (i.e. PERL, TCL, or Python).
• Experience with Hardware validation techniques (i.e., formal Verification, Test and Function Verification).

Preferred Qualifications:
• Post graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Experience with Industry standard protocols (i.e. PCIE, USB, DRR, etc)
• Experience with interaction of computer hardware with software
• Experience with Low power/UPF implementation/verification techniques.
• Experience with Timing Analysis / Physical Verification / Formal verification techniques.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.