Master Thesis (f/m/x)

As advanced semiconductor technologies continue to scale, SRAM arrays and register files become increasingly susceptible to radiation-induced soft errors. These transient faults can lead to Silent Data Corruption (SDC), one of the most critical reliability challenges in modern processors. Existing Soft Error Rate (SER) estimation techniques often rely on static assumptions, simplified analytical models, or fault injection campaigns that do not accurately represent the behavior of real applications under realistic operating conditions. The proposed work aims to address this limitation by developing a workload-aware methodology for measuring architectural soft-error vulnerability directly within the design environment. The central idea is to instrument memory arrays at the RTL level with functionally transparent monitoring logic that captures detailed usage characteristics while executing realistic workloads. By combining these measurements with cycle-accurate hardware-accelerated simulation, the project generates a comprehensive exposure profile for each memory structure and derives realistic vulnerability metrics that are directly applicable to processor reliability design. The central idea is to instrument memory arrays at the RTL level with functionally transparent monitoring logic that captures detailed usage characteristics while executing realistic workloads. By combining these measurements with cycle-accurate hardware-accelerated simulation, the project generates a comprehensive exposure profile for each memory structure and derives realistic vulnerability metrics that are directly applicable to processor reliability design. What you bring 🎓 Matriculation at an university in Business Informatics, Computer Science, or a related field 👉 Completed Bachelor degree and practical experiences in hardware/software development Germany Project Management Hybrid Internship Ehningen, DE