Sr. ASIC Physical Design Engineer

As a block-level Physical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII. Your responsibilities include: 

Responsibilities: 

• Implement physical design at the large SoC block level from RTL to GDSII, creating a design database ready for manufacturing. 

• Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub-chips at a large SoC level. 

• Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement. 

• Build block level floorplan, including block pins, macro placement and alignment, power grid, etc. 

• Develop the block-level clock network and clock structure in collaboration with clock experts. 

• generating block/chip-level static timing constraints. 

• Arrange, analyze, and optimize feedthrough and repeaters among all blocks

• Perform block-level place and route, including custom place & route, ensuring the design meets timing, area, power constraints, and all sign-off criteria. 

• Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification. 

• Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements. 

• Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations. 

• Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts. 

Minimum Qualifications: 

Education: 

• BS degree in electrical engineering, computer engineering, or a related field with 3+ years of experience in block or full-chip physical design, or 

• MS degree in the above fields with 2+ years of related experience. 

Technical Expertise: 

• Deep design experience in large SoC designs, including IP integration.

• Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough. 

• Experience in implementing power-grid and clock network at block level. 

• Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes. 

• Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level. 

• Experience in custom place and route. 

• Exposure to 2.5D/3D packaging is preferred. 

• High performance and large chip design experience is preferred. 

• Exposure to DFT is preferred. 

• Proficiency in writing Linux shell scripts in Perl, TCL, and Python. 

• Real chip tapeout experience in 7nm and/or below with a successful signoff track record. 

• Self-motivated with strong problem-solving and debugging skills. 

• Ability to work effectively in a dynamic group environment.