Loading
G
Senior SoC Hardware Quality and Reliability Engineer
GoogleWest Memphis, AR, USASenior8+ years
Apply Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, related fields, or equivalent practical experience.
- 8 years of experience in hardware engineering, with a focus on authoring technical specifications, reviewing electrical layouts, and driving verification of semiconductor tests or validation platforms.
- Experience driving deliverables and managing quality standards with external layout vendors, board design houses, or hardware component suppliers across multiple global geographies.
- Experience working within specialized semiconductor reliability or test laboratories including configuring component Burn-In ovens, high-power stress load boards, ESD simulators, and Latch-Up test setups.
- Experience managing engineering hardware delivery schedules, tracking cross-functional milestones, and meeting New Product Introduction (NPI) timelines.
Preferred qualifications:
- Master's degree in Electrical Engineering, Materials Science, or related fields.
- Experience managing the design execution cycle of complex multi-layer test vehicles through third-party design houses or layout vendors from concept sign-off to laboratory delivery.
- Experience defining and verifying electrical correlation baselines between environmental stress setups and High-Volume Manufacturing (HVM) ATE environments.
- Deep familiarity with JEDEC silicon qualification hardware standards and how they dictate physical board testing constraints.
- Strong background analyzing the quality of stress factors, including power distribution networks (PDN), signal integrity degradation across extended thermal loops, and transient load behavior during reliability cycles.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Own technical specifications, architectural definitions, and physical power-on of custom qualification vehicles (HTOL load boards, ESD fixtures, latch-up rigs). Drive external layout vendors to achieve seamless electrical correlation with ATE environments.
- Govern execution quality of applied stresses, define electrical, thermal, and telemetry parameters on test vehicles to ensure uniform, valid stress profiles without unintended overstress or setup artifacts.
- Lead the end-to-end engineering delivery lifecycle for qualification hardware, map and drive critical cross-functional dependencies across internal validation and product engineering teams to ensure on-time readiness.
- Serve as the primary technical interface for external PCB layout houses, fabrication shops, and component suppliers; manage design reviews, track lead times, and enforce delivery schedules.
- Lead laboratory troubleshooting for qualification hardware anomalies; isolate setup/socket faults from true silicon failures and drive supplier corrective actions (CAPA) when board excursions occur.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.