FPGA Engineer (New Hire Sign-On Bonus Available)

Basic Qualifications

Education Requirements:

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience.

 

Clearance Requirements:

Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

 

 

Responsibilities for this Position

New Hires Eligible for Sign-On Bonus

 

Duties and Tasks:

• Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
• Determines architecture, system simulation and detailed design approach
• Defines module interfaces and all aspects of device design and simulation
• Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization
• Creates test and simulation plans that establish functional criteria
• Verifies test results and analyzes performance
• May also review vendor capabilities, foundry technologies, device libraries and simulation tools

 

Knowledge, Skills and Abilities:

• Solid proficiency and able to perform all responsibilities associated with the position
• Grasps and applies new information quickly
• Solid ability to handle more complex assignments
• Shows initiative on assignments, exercises independent judgment and professionally executes projects with little direction
• Solid use of ASIC/FPGA concepts, principles, and theories
• Solid understanding of ASIC/FPGA engineering processes
• Keeps abreast of technology trends in ASIC/FPGA
• Solid awareness of business objectives and Engineering’s role in achieving
• Solid knowledge in Microsoft Office applications
• Solid knowledge in ASIC/FPGA design tools
• Solid written and verbal communications skills
• Ability to think creatively
• Ability to multi-task
• Solid skill in communicating issues, impacts, and corrective actions
• Solid understanding of basic earned value, Cost Account Management (CAM), and Variance Report generation
• Solid ability to recognize and clearly report information relevant to sound ASIC/FPGA design
• Identifies opportunities to apply AI for continuous improvement and innovation

Salary Note

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range

USD $114,489.00 - USD $120,750.00 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans