About Code Metal

Code Metal is redefining code translation for mission-critical industries, helping defense partners move more quickly and reliably from algorithm to silicon. Our platform accelerates deployment of DSP, RF, communications, and embedded signal processing algorithms onto heterogeneous compute targets, including GPUs, FPGAs, ASICs, and edge SoCs. We also support automotive, aerospace, and semiconductor partners deploying complex algorithms onto constrained hardware with speed and rigor.

Senior HLS Engineer Role

Code Metal is in the business of transpiling between different languages. This includes the transpilation tools enabled by AI and modern verification techniques — bridging the gap between algorithm development and deployment to embedded systems.

We are currently looking for a senior high-level synthesis engineer interested in architecting and expanding our capabilities towards creating production-ready RTL from high-level algorithm descriptions. This role focuses on HLS integration, architectural transformation, and vendor-agnostic RTL generation. You will be joining a team that values technical rigor, ownership, and collaboration across disciplines.

Responsibilities

• Build a vendor-agnostic HLS integration layer supporting multiple backends

• Develop post-HLS readability and optimization passes to produce human-auditable RTL

• Leveraging Agentic AI and verification capability within Code Metal

• Contribute to CI/CD qualification including automated RTL simulation, functional verification, and regression testing

• Evaluate HLS tool output quality, track vendor licensing requirements, and inform toolchain strategy

Required Qualifications

• 5+ years of hands-on experience with High-Level Synthesis, including at least one commercial HLS tool (Catapult, Vitis HLS, Stratus, or equivalent)

• Solid HLS modeling background regarding fixed-point arithmetic, bit-accurate types, synthesis pragmas and modeling trade-offs

• Scripting experience in Python for development, toolchain automation and testing

• Strong debugging and problem-solving skills

• Experience with simulation and functional verification flows

Preferred Qualifications

• Experience using Linux-based development environments

• Solid understanding of RTL / VHDL

• Understanding of FPGA architectural capabilities and constraints

• Knowledge of verification methodologies and testbench development

• Experience with DSP algorithms and applications using Python/MATLAB

Nice to Have:

• Bonus: Interest in or familiarity with LLM-assisted code transformation and readability tooling

• Experience with Git-based development workflows and CI/CD environments

Benefits

• Pay depends on experience, but we strive to be at the upper end of the salary range

• Health care plan with 100% premium coverage, including medical, dental, and vision

• 401k with 5% matching

• Paid Time Off (uncapped vacation, plus sick and public holidays)

• Flexible hybrid or remote work arrangement

• Relocation assistance for qualifying employees

Wage Transparency - The salary range for this role is not a guarantee of compensation or salary, as the final offer amount may vary based on factors including, but not limited to, individual proficiency, skills, experience, and location.

We are an equal opportunity employer. US Citizenship may be required for certain project assignments involving security clearance.

Pursuant to the San Francisco Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.