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ASIC Design Engineer — Pixel IP
AppleSunnyvale, California, United States$129,300 - $194,70010+ years
Apply Do you love creating elegant solutions to highly complex challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices!
In this highly visible role, you will be at the center of the Pixel IP design effort to capture and display beautiful images and video. You will collaborate with all disciplines, making a critical impact getting functional products to millions of customers quickly.
As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing engines. Apply your knowledge of computer architecture and digital design to create digital signal processing pipelines for capturing, improving, compressing, decompressing, and displaying digital still images and video.
In this front-end design role, your tasks will include:
• Design digital hardware by writing high-quality RTL or using a high-level synthesis methodology, with embedded assertions and cover points.
• Writing detailed micro-architectural specifications.
• Collaborating with cross-functional teams to explore solutions that maximize performance while minimizing power and area.
• Synthesizing your design and optimize for power, timing, and area.
• Working closely with design verification and formal verification teams to debug and verify functionality and performance.
• Working independently and manage deliverables to align with the project goals and support cross-functional engineering efforts.
- Bachelors Degree in EE/CE and 10+ years of relevant industry experience.
- Extensive experience in SoC front-end ASIC RTL digital logic design using Verilog and System Verilog.
- Prefer deep experience in media, video, pixel, or display designs.
- Practiced in low-power design techniques such as clock- and power-gating.
- Extensive experience working cross-functionally with architecture, design, and verification teams to specify, design, and debug designs.
- Strong collaboration skills with excellent written and verbal communication skills.
- Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
- Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, and logic equivalence checks.
- Industry exposure to and knowledge of ASIC design methodology including familiarity with relevant scripting languages (Python, Perl, TCL).