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Wireless Radio Verification Engineer
AppleSan Diego, California, United States$122,700 - $214,300
Apply Join Apple's Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. You'll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies—enabling multi-gigabit wireless technology connecting the world!
As a Wireless Radio Verification Engineer, you'll verify Radio digital controllers combined with RF subsystems that enable exceptional wireless performance. You'll develop verification environments for complex radio control / transceiver paths spanning PLLs, DAC / ADC data paths, power management, and co-existence mechanisms. This role emphasizes digital verification while bridging to RF/analog domains—you'll work closely with Design, RF, PHY, and Systems teams to understand radio specifications and develop comprehensive test strategies. You'll own subsystem verification from test planning through coverage closure, building testbench components and scenarios that exercise complex radio control sequences and operating modes.
- Verify Radio digital controllers or subsystems from test planning, environment bring-up, through feature closure.
- Develop UVM testbench environments, bus functional models, and infrastructure for radio control and datapath subsystems.
- Implement constrained random scenarios exercising radio protocols, control sequences, and state machine interactions.
- Collaborate on digital + mixed-signal verification using SystemVerilog analog behavioral and/or DMS/real-number models to validate radio control paths.
- Drive closure by tracking regressions, debugging issues, and addressing coverage gaps.
- Partner with cross-functional Design, RF, and Systems teams to define verification strategy.
- Develop Python automation supporting verification flows and regression infrastructure.
- Minimum requirement of a bachelor’s degree.
- Understanding of ASIC verification flows with SystemVerilog including UVM testbench development, scenario creation, and RTL simulation.
- Experience developing verification environments, bringing up designs in simulation, and debugging functional issues.
- Experience with digital design fundamentals Verilog or VHDL.
- Experience with scripting languages such as Python, or similar.
- Strong problem-solving abilities and collaborative approach to engineering challenges.
- Experience with digital controllers, subsystems, or data paths.
- Experience with constrained random testing, functional coverage implementation, UVM methodology, and assertion-based verification.
- Exposure to mixed-signal modeling concepts including real-number modeling.
- Exposure to RF/analog system design such as LNAs, Mixers, PLLs, amplifiers, LDOs, DAC / ADCs.
- Proficiency with Python, Perl, Bash or similar scripting for automation.
- Great teammate with excellent communication skills and desire to seek diverse technical challenges.
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