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EMIR/Power Integrity Methodology Engineer
AppleCupertino, California, United States$150,400 - $277,6003+ years
Apply The SOC hardware development team is looking for a motivated candidate to fill a full-time position. The primary role is to verify the integrity of the power grid. This includes setting the static IR drop and instantaneous voltage drop (IVD) targets for multiple SOCs and verifying that targets are met.
The main responsibility of this role is to provide initial assessment of power grids for new chips and new technology, define settings for power grid simulations, and verify power grid integrity. The candidate will be expected to:
• Develop experimental flows for power integrity analysis tools using CAD flow — simulations include input from timing, package, and board level abstraction.
• Drive initial assessment of static IR drop, instantaneous voltage drop (IVD), and power grid noise for jitter analysis in power grids.
• Determine settings for SOC analysis for different types of grids, including electro-migration/IR/IVD analysis.
• Work with physical design and timing teams to analyze simulation results, verify that power grid integrity targets are met, and enhance simulation flow.
• Explore new tools and methodologies for power grid integrity.
- A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience.
- The candidate should have experience in ASIC design methodology with an emphasis on power grid analysis.
- Expert user of Redhawk, Voltus, or other equivalent power grid analysis tool.
- Strong understanding of power grid integrity and reliability.
- Experience in physical design implementation, STA preferred.
- Strong communication skills and ability to work on a team since the position requires interfacing with cross functional teams.
- Experience in spice simulations and library characterization.
- Good technical writing skills.
- 3+ years of experience preferred.