CPU Gate Level Synthesis Engineer

Santa Clara, California, United StatesHardware$181,100 - $318,40010+ years

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple’s Silicon Engineering Group (SEG) is looking for a hardworking engineer for our CPU Gate Level Synthesis role to assess and optimize design quality. In this role, the candidate would be a part of Apple’s industry-leading CPU design team, working in a multi-functional role to ensure that our CPUs meet the highest standards for performance, power and area.

As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running RTL to gate level synthesis and finding opportunities to optimize timing, power, and area for micro-architectural features. You will collaborate with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, RTL optimization and power analysis. Responsibilities include but are not limited to: • Early RTL health assessment to detect potential timing/gate-depth issues and collaborating with the RTL & physical design teams in exploring solutions • Early stage power estimation and validation for new micro-architectural features • Enhancing synthesis flows for good correlation to post-route to ensure high fidelity of synthesis-based feedback • Work closely with DFT teams to ensure seamless integration of scan chain, ATPG, and MBIST into the synthesis flow • Partner with timing team to enable constraints generation at top levels • Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs • Track and analyze PPA trends through project cycle

Minimum BS and 10+ years of relevant industry experience
Experience in digital logic design, RTL synthesis, and physical design

The ideal candidate should possess CPU implementation experience
Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow optimization
Strong problem-solving, debugging, and collaboration skills in a fast-paced environment

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.

$147,400 - $272,100

Speech Scientist / Engineer (Interspeech 2022)Cupertino, California, United StatesSoftware and Services

RAN1/RAN4 Standards EngineerBeijing, Beijing, ChinaHardware

Display Metrology EngineerShenzhen, Guangdong, ChinaHardware

Molding Process EngineerShanghai, Shanghai, ChinaHardware

Molding Process EngineerShenzhen, Guangdong, ChinaHardware

CPU Gate Level Synthesis Engineer

Similar Jobs