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CPU Design Timing Engineer
AppleBeaverton, Oregon, United States10+ years
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Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:
• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
• Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU
- Minimum BS and 10+ years of relevant industry experience
- Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains
- Experience with one of the following static timing tools: Primetime or Tempus
- Experience with cross talk, noise, OCV, uncertainty, and derate methodology
- Experience with script writing and debugging in one or more of the following languages: TCL, Perl, Python
- Implementation experience on high performance CPU designs
- Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
- Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
- Knowledge of static timing tools and flows including how to handle multiple clock and power domains
- Knowledge of device physics especially aspects which impact timing: cross talk, noise, OCV, uncertainty and derate methodology
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