IC Design Exploration Intern

As an AMD [intern/co-op], you’ll be placed at the epicenter of the AI ecosystem, working alongside experts and industry pioneers. You’ll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide. Whether you’re an undergrad or a PhD student, your contributions matter—and your experience here will be a launchpad for what comes next.

LOCATION: Singapore

CRITERIA: Current students studying in Universities which are based in Singapore

INTERNSHIP DURATION: The internship will begin on either 4 May 2026 or 20 July 2026, and will end on 4 Dec 2026. There is an option to extend the internship, with the extended period concluding on a fixed date of 18 Dec 2026.

Intern - IC Design Exploration

WHAT YOU CAN EXPECT TO LEARN:

• Gain industry experience working on the latest technology process nodes.
• Join us and learn about how fulfilling a career in IC design can be!
• As we have various disciplines within IC design, we would get to know you better through the application process and assign you to the most suitable team to best fit you!

PROJECT OVERVIEW:

Jump start your IC design journey by being part of a dynamic team covering many areas including but not limited to analog design and implementation, digital design and implementation, functional verification, post-silicon validation, and many more!

You will be part of the SerDes Technology team and get the opportunity to collaborate with our teams around the globe. Being alongside engineers across different disciplines means that you would get a better understanding of the differences between different disciplines so that you are able to make an informed decision on which path to pursue when you join us after your graduation.

KEY RESPONSIBILITIES:

• First few weeks
  • Get to know more about Singapore Design Team at AMD
  • Strengthen foundational technical IC design knowledge
  • Get comfortable working independently as well as in a team environment across multiple geographical sites.
• Next few months
  • Develop soft skills such as communication and presentation by participating in technical discussions and conduct knowledge sharing sessions
  • Be able to appreciate the considerations when making engineering judgement decisions
  • Work on projects as part of specialization (see details in section below)
• Throughout the internship
  • Participate in company/department events, social events, recreation events, etc

SPECIALIZATIONS: (would be attached to one of the following)

• Analog design
  • Design and development of high speed analog and mix signal circuit and its auxiliary circuit block design (112Gbps and above) in advanced technology node (3nm, 7nm)
  • Use, simulate and analyze log and report generated from EDA tools and make design trade-off to get the required results within the scheduled milestones
  • Learn the architecture and design of SERDES block (Transmitter, receiver, pll etc)
  • Basic scripting and programming (Unix, Pytthon, Perl)
  • Familiarization with IC design tools (Cadence ADE/Spectre, Synopsys Hspice/XA, etc)
  • Learn and understand IC design flow to implement circuit design
  • Candidates will have the opportunity to explore cross function experience eg RTL/Layout/STA/Verification
• Analog layout implementation
  • Layout implementation in high speed circuit and its auxiliary circuit block design (112Gbps and above) in advanced technology node (3nm, 7nm)
  • Perform various physical verification checks such as Layout-versus-Schematic (LVS) and Design Rule Check (DRC) to meet circuit function, performance, and process requirements
  • Understand basic Process Design Rules and differences in metal schemes.
  • Basic scripting and programming (Unix, Pytthon, Perl)
  • Familiarization with IC design tools (Cadence Virtuoso , Calibre, etc)
  • Learn and understand IC design flow to implement layout design
  • Candidates will have the opportunity to explore cross function experience eg RTL/Circuit /PnR/STA/Verification
• Analog static timing analysis
  • Developing timing models for advanced technology nodes mixed signal circuits and complex standard cells. 
  • To enable a good static timing analysis run, work with various stakeholders (design, layout and integration team) to build constraints, tune design hierarchy level, review timing report to have a timing model generated.
  • To ensure quality of models generated, developing and updating quality check scripts.
  • Release and maintenance of the timing model databases.
  • Evaluate best in class EDA tools and flow in the industry.
• Digital design
  • Roles
    • Digital Design
      • Low Power design explorations
      • Design digital logic blocks in Verilog (RTL)
      • Develop testbench and functional verification of developed digital logic blocks.
    • Silicon validation
      • Develop Emulation platform using Python and CocoTB (https://www.cocotb.org/ )
      • Post silicon validation, testing and debug of block functionality on prototype silicon.
    • Next generation RTL/AI tool
      • Explore new approaches to improve RTL quality and productivity.
      • Explore AI/ML to improve RTL methodology.
  • Preferred skills
    • Good fundamental of digital logic design is preferred.
    • Experience in Verilog and/or VHDL is preferred.
    • Good programming/scripting skills (Python, OOP concepts, Perl, etc) is preferred.
• Digital implementation
  • Get proficient working in UNIX/LINUX environment to use Electronic Design Automation (EDA) tools such as Synopsys Design Compiler, IC Compiler 2, Fusion Compiler
  • Implement P&R designs using the latest technology from 3nm to 16nm node process
  • Develop and implement plans to synthesize and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
  • Design complex clock structure to meet tight skew requirements
  • Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
  • Ensure the implemented design meets all DRC required for process node below 16nm as well as DFM.
  • Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
• Digital static timing analysis
  • Get proficient working in UNIX/LINUX environment to use Electronic Design Automation (EDA) tools such as Synopsys PrimeTime
  • Develop timing constraints to enable static timing analysis
  • Simulate and analyse logs/reports generated from EDA tools (mainly ICC2 and Primetime) and make design trade-off to get the required results within the scheduled milestones.
• Functional verification
  • Roles
    • Functional verification of SerDes and/or Security IP design blocks
      • Participate in testbench environment design and implementation in SystemVerilog/UVM-based framework and/or Python-based framework.
      • Execute and manage regressions and work closely with design team to debug, identify, and resolve design bugs.
      • Perform coverage analysis to ensure all design features are verified.
    • Simulation framework development
      • Participate in development of automation and/or hardware acceleration to improve engineering efficiency and productivity.
      • Participate in exploration of incorporating AI/ML into automation framework.
    • Next generation verification methodology exploration
      • Participate in exploration of new approach to improve verification quality and productivity.
      • Participate in exploration of incorporating AI/ML into verification methodology.
  • Preferred skills
    • Good fundamental of digital logic design is preferred.
    • Experience in SystemVerilog and/or UVM is preferred.
    • Good programming/scripting skills (Python, C/C++, Perl, Ruby, Java, etc) is preferred.
    • Experience in AI/ML related project is preferred.
• Post-silicon validation
  • Roles
    • Post silicon validation of high speed SerDes.
    • SerDes bring up, functional verification and performance optimization.
    • Develop validation methodology and automation scripting to characterize the latest SerDes design.
    • Work with design engineer on SerDes silicon issue debug.
    • Tune and optimize SerDes configuration and validate SerDes for meet various industrial compliance standards in PVT environment.
  • Preferred skills
    • Strong programming/scripting skills (eg. Python, C/C++, Perl, TCL et.) for firmware development, test methodology development and test automation
    • Knowledge of common lab equipment, including BERT, analyzers, oscilloscopes, PNA/VNA etc.

WHO ARE WE LOOKING FOR:

A self-driven individual with a willingness to learn, resourceful and passionate about technology. Willingness to learn with a good attitude. Willing to work hard and play hard!

RELEVANT SKILLSETS:

• Scripting skills (eg. Perl, TCL, shell, Python) beneficial
• Fast learner and ready to solve problems
• Excellent problem-solving and communication skills
• Ability to work collaboratively in a team-oriented environment

ACADEMIC CREDENTIALS:

• Degree/Master/PhD in Electronics/Electrical/Computer Engineering/Computer Science

Note:

• Please ensure that you can provide a placement/support letter from your school covering the entire internship period.

#LI-SP