PD Architect

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

PMTS SILICON DESIGN ENGINEER

THE ROLE: 

As a member of the S3 India physical design team, you will help bring to life cutting-edge designs. As a member and lead of the Physical design implementation team, you will work closely with the SOC architects, Physical design architects, design leads, IP teams, Physical Design leads and PD/STA engineers to achieve first-pass silicon success. You will be expected to lead design implementation and convergence activities in the backend from a PnR implementation perspective.

In this position as a Physical Design Expert, you will be part of a world-class team developing groundbreaking high-performance ASICS & APU/dGPU designs. These products are targeted for Game Consoles, High-end Discrete Graphics, Thin and Light Laptops, Artificial Intelligence solutions for Inference, Telecommunication, Automotive applications and more. This is a great opportunity to join a talented team that is well-invested in the implementation of futuristic designs in advanced process nodes.

THE PERSON:

As a principal member of the technical staff (PMTS), you will be responsible for driving a team of silicon design engineers for the successful delivery of project tape-outs from RTL-GDS.

You will use your knowledge of Physical design to lead a complete set of Backend activities, specifically PnR, timing, verification and signoff, including IP integration and full-chip aspects.

This position requires a detail-oriented candidate who possesses good communication skills and can handle/work with teams.

KEY RESPONSIBILITIES:

• Lead the physical design team for implementation and convergence of highly complex tiles.
• Will be responsible for delivery of GDS starting from RTL, including sign-off and physical verification.
• Collaborate with cross-functional teams to drive continuous improvements for achieving better PPA.
• Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows.
• Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle.
• Drive methodology development ideas/forums.
• Collaborate with CAD and EDA vendors to further strengthen AMD and S3 PD closure methodology.
• Provide technical direction, guidance, and Support to the engineering team.

 PREFERRED EXPERIENCE:

• Experienced PD professional with a minimum of 15 years of industry experience in the Physical design domain (RTL to GDS, STA, Physical verification, timing signoff, tapeout).
• Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification.
• Well-versed with Physical Design verification signoff techniques such as Formal Equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc.
• Good understanding of Power, Performance and Area (PPA) optimisation techniques.
• Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design.
• Excellent presentation and inter-communication skills.

Qualifications:

• B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering.
• Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 3 tape-outs.
• Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools.
• #LI-BM2 

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.